CS2354 Advanced Computer Architecture Anna University PPT collections
UNIT I INSTRUCTION LEVEL PARALLELISM
ILP Concepts and challenges Part2
Hardware and software approaches
Dynamic scheduling
Speculation
Compiler techniques for exposing ILP
Branch prediction.
UNIT II MULTIPLE ISSUE PROCESSORS
VLIW & EPIC
Advanced compiler support
Hardware support for exposing parallelism
Hardware versus software speculation mechanisms
IA 64 and Itanium processors
Limits on ILP
UNIT III MULTIPROCESSORS AND THREAD LEVEL PARALLELISM
Symmetric and distributed shared memory architectures
Performance issues
Synchronization
Models of memory consistency
Introduction to Multithreading.
UNIT IV MEMORY AND I/O
Cache performance
Reducing cache miss penalty and miss rate
Reducing hit time
Main memory and performance
Memory technology.
Types of storage devices
Buses
RAID
Reliability, availability and dependability
I/O performance measures
Designing an I/O system.
UNIT V MULTI-CORE ARCHITECTURES
Software and hardware multithreading Part2
SMT and CMP architectures
Design issues
Case studies
Intel Multi-core architecture
SUN CMP architecture
Heterogenous multi-core processors
case study: IBM Cell Processor
UNIT I INSTRUCTION LEVEL PARALLELISM
ILP Concepts and challenges Part2
Hardware and software approaches
Dynamic scheduling
Speculation
Compiler techniques for exposing ILP
Branch prediction.
UNIT II MULTIPLE ISSUE PROCESSORS
VLIW & EPIC
Advanced compiler support
Hardware support for exposing parallelism
Hardware versus software speculation mechanisms
IA 64 and Itanium processors
Limits on ILP
UNIT III MULTIPROCESSORS AND THREAD LEVEL PARALLELISM
Symmetric and distributed shared memory architectures
Performance issues
Synchronization
Models of memory consistency
Introduction to Multithreading.
UNIT IV MEMORY AND I/O
Cache performance
Reducing cache miss penalty and miss rate
Reducing hit time
Main memory and performance
Memory technology.
Types of storage devices
Buses
RAID
Reliability, availability and dependability
I/O performance measures
Designing an I/O system.
UNIT V MULTI-CORE ARCHITECTURES
Software and hardware multithreading Part2
SMT and CMP architectures
Design issues
Case studies
Intel Multi-core architecture
SUN CMP architecture
Heterogenous multi-core processors
case study: IBM Cell Processor